Electronic dispersion compensation within optical communications using reconstruction

ABSTRACT

Electronic dispersion compensation within optical communications using reconstruction. Within a communication system that includes any optical network portion, segment, or communication link, etc., that optical component/portion of the communication system is emulated within the electronic domain. For example, in a communication device having receiver functionality, deficiencies that may be incurred by the at least one optical portion of the communication system are compensated in the electronic domain of the communication device having the receiver functionality by employing reconstruction logic and/or circuitry therein. Multiple decision feedback equalizers (DFE) circuitries, implemented in the electronic domain, may be employed to provide feedback from different portions of the receiver functionality in accordance with performing compensation of optical incurred deficiencies (e.g., dispersion, non-linearity, inter-symbol interference (ISI), etc.). Within a communication device&#39;s receiver portion, equalization and compensation is performed in the electronic domain as adapted for high speed applications and higher order modulation schemes.

CROSS REFERENCE TO RELATED PATENTS/PATENT APPLICATIONS ProvisionalPriority Claims

The present U.S. Utility Patent Application claims priority pursuant to35 U.S.C. §119(e) to the following U.S. Provisional Patent Applicationwhich is hereby incorporated herein by reference in its entirety andmade part of the present U.S. Utility Patent Application for allpurposes:

-   1. U.S. Provisional Application Ser. No. 61/237,579, entitled    “Electronic dispersion compensation within optical communications    using reconstruction,” filed Aug. 27, 2009, now expired.

INCORPORATION BY REFERENCE

The following U.S. Utility Patent Application is hereby incorporatedherein by reference in its entirety and is made part of the present U.S.Utility Patent Application for all purposes:

-   1. U.S. Utility patent application Ser. No. 11/837,278, entitled    “Electronic dispersion compensation utilizing interleaved    architecture and channel identification for assisting timing    recovery,” filed Aug. 10, 2007, now issued as U.S. Pat. No.    7,961,781, on Jun. 14, 2011, which claims priority pursuant to 35    U.S.C. §119(e) to the following U.S. Provisional Patent Application    which is hereby incorporated herein by reference in its entirety and    made part of the present U.S. Utility Patent Application for all    purposes:-   a. U.S. Provisional Application Ser. No. 60/840,123, filed Aug. 25,    2006, now expired.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The invention relates generally to optical communication systems; and,more particularly, it relates to performing electronic compensation foreffects incurred by optical components within a communication system.

2. Description of Related Art

Data communication systems have been under continual development formany years. Certain communication systems include at least one opticalnetwork portion, segment, or communication link, etc. therein. In suchcommunication systems that include such an optical portion thereof, suchoptical components therein may introduce certain deleterious effectswhich may generally be referred to as optical incurred deficiencies(e.g., dispersion, non-linearity, inter-symbol interference (ISI),etc.).

In addition, as various manufacturers of components move to provisioncommunication devices that operate using higher data rates (bit rates)as well as more advanced modulation types (e.g., duobinary, differentialphase shift keying (DSPK), differential quadrature phase shift keying(DQSPK), etc.), the magnitude of such optical incurred deficienciesnecessarily can become exacerbated, and the overall effectiveness andoperation of the communication system can suffer.

Within the prior art, the current means by which equalization is beingperformed simply cannot scale adequately with such higher data rates(bit rates) and more advanced modulation types. There exists a need inthe art for a more effective means to deal with and compensate for suchoptical incurred deficiencies within such a communication system thatincludes at least one optical portion.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theSeveral Views of the Drawings, the Detailed Description of theInvention, and the claims. Other features and advantages of the presentinvention will become apparent from the following detailed descriptionof the invention made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 and FIG. 2 illustrate various embodiments of communicationsystems.

FIG. 3 illustrates an embodiment of an optical duobinary (ODB)communication system.

FIG. 4 illustrates an embodiment of an electronic dispersioncompensation (EDC) circuitry.

FIG. 5 illustrates an embodiment of an EDC circuitry for an ODB receivercommunication device.

FIG. 6 illustrates an embodiment of an EDC circuitry for an ODB receivercommunication device that employs two separate decision feedbackequalizers (DFEs).

FIG. 7 illustrates an embodiment of an optical differential phase shiftkeying (DSPK) communication system.

FIG. 8 illustrates an embodiment of an EDC circuitry for a DSPK receivercommunication device that employs two separate DFEs.

FIG. 9 illustrates an embodiment of a constellation plane fordifferential quadrature phase shift keying (DQSPK) modulation.

FIG. 10 illustrates an embodiment of an EDC circuitry for a DQSPKreceiver communication device that employs three separate DFEs.

FIG. 11A and FIG. 11B illustrate various embodiments of methods forperforming electronic dispersion compensation in the electronic domainusing reconstruction for a communication device implemented within anoptical communication system.

DETAILED DESCRIPTION OF THE INVENTION

The goal of digital communications systems is to transmit digital datafrom one location, or subsystem, to another either error free or with anacceptably low error rate. As shown in FIG. 1, data may be transmittedover a variety of communications channels in a wide variety ofcommunication systems: magnetic media, wired, wireless, fiber, copper,and other types of media as well. Certain types of communication systemsmay also include various network segments, communication links, etc.composed of various types of media. For example, a communication systemmay include a satellite network segment, a wired network segment, awireless network segment, and an optical network segment. Variousembodiments of a communication system may include at least one opticalnetwork segment (e.g., at least one optical communication link).

Within many types of communication systems (e.g., the telecommunicationsindustry), there are efforts to move to higher and higher data rates(bit rates) and more advanced modulation types. For example, withrespect to long range and long haul telecommunications, there areefforts in the industry to increase to bit rates to 40 Gbit/s, 100Gbit/s, and even greater rates over very long distances (e.g., greaterthan 1000 km). In addition, there is movement in the industry to try toemploy advanced modulation types such as duobinary, differential phaseshift keying (DSPK), and differential quadrature phase shift keying(DQSPK).

Optical duobinary transmission (ODB) offers some benefits forcommunication systems employing bit rates of 10 Gbit/s and aboveincluding improved dispersion tolerance and increased spectralefficiency (e.g., see references [1, 2]). There has been much interestin the art to address various concerns related to encoding, decoding,modulation, and transmission for an ODB communication system.Oftentimes, modulation in such communication systems is achieved using aMach-Zehnder modulator biased at its null point. Therein, three levelsof signal in terms of electric field (e.g., −1, 0 +1) are employed. Interms of optical power, only two signal levels are transmitted.

Optical DPSK (sometimes alternatively referred to as oDPSK) consists inrepresenting a logical “0” by a phase the optical wave/signal equal to 0and a logical “1” by a phase of π or 180 degrees. By ensuring that theoptical intensity remains constant, such a modulation type has a hightolerant towards non-linearities. DPSK is closely related to ODB (e.g.,see reference [3]) and can be considered as a duobinary signal.

DQPSK encodes data arranged in di-bits (groups of two bits) into one offour phase difference values, such as: 00→0, 01→π/2, 11→π, 10→−π/2. Thismay be considered as two DPSK channels operating in parallel with onearm subject to a π/2 or 90 degrees phase shift to put the two fields inquadrature (e.g., see reference [4]).

On the other hand, traditional optical receivers typically perform aminimal amount of signal processing. Recently, electronic compensationof channel impairments such as chromatic or polarization-mode dispersion(PMD) have been discussed in accordance with attempts to improveperformance and brings flexibility of signal processing to the opticalcommunication systems (e.g., see references [5, 6]).

An optical receiver communication device may be implemented to performthe optical to electronic (or electrical) conversion of signals using aphoto detector or photo diode; such devices are sensitive to the opticalpower of a received signal (e.g., by producing a photo-current thatcorresponds to the optical intensity/power of the received opticalsignal that arrives at the photo detection surface).

In an ODB communication system, though three levels of signals have beentransmitted, only two different levels are received from the perspectiveof photo detection. Therefore, a conventional or prior art type ofelectronic dispersion compensation (EDC) circuit circuitry has asignificant drawback to compensate the difference between −1 and +1signals.

In the optical DPSK communication system, the transmitted field over theoptical fiber is a differential precoded signal. At the receiver side ofthe optical communication channel, the differential coded signal isdemodulated using a delay line interferometer and balanced detector ordirect detector. Therefore, a conventional EDC circuitry does notcompensate for the optical field transmitted over the fiber directly.The conventional EDC circuitry for an optical DQPSK communication systemsuffers the similar problem.

Herein, a novel EDC circuitry and EDC approach is presented that isoperative to compensate fully for any incurred channel impairments andis applicable to each of an ODB communication system, a DPSKcommunication system, and a DQPSK communication system. This isachieved, at least in part, by employing a reconstruction circuit thatoperates to perform such EDC in the electronic domain. An electronicsignal is generated that is emulative of an optical signal that isreceived from the optical communication link.

FIG. 1 and FIG. 2 are diagrams illustrate various embodiments ofcommunication systems, 100 and 200, respectively.

Referring to FIG. 1, this embodiment of a communication system 100 is acommunication channel 199 that communicatively couples a communicationdevice 110 (including a transmitter 112 having an encoder 114 andincluding a receiver 116 having a decoder 118) situated at one end ofthe communication channel 199 to another communication device 120(including a transmitter 126 having an encoder 128 and including areceiver 122 having a decoder 124) at the other end of the communicationchannel 199. In some embodiments, either of the communication devices110 and 120 may only include a transmitter or a receiver. There areseveral different types of media by which the communication channel 199may be implemented (e.g., a satellite communication channel 130 usingsatellite dishes 132 and 134, a wireless communication channel 140 usingtowers 142 and 144 and/or local antennae 152 and 154, a wiredcommunication channel 150, and/or a fiber-optic communication channel160 using electrical to optical (E/O) interface 162 and optical toelectrical (O/E) interface 164)). In addition, more than one type ofmedia may be implemented and interfaced together thereby forming thecommunication channel 199.

To reduce transmission errors that may undesirably be incurred within acommunication system, error correction, and channel coding schemes areoften employed. Generally, these error correction and channel codingschemes involve the use of an encoder at the transmitter and a decoderat the receiver. Of course, any such communication device implementedwithin such a communication system as described herein, or other type ofcommunication system, may itself be transceiver type communicationdevice that includes an encoder module therein for encoding signals tobe transmitted (e.g., encoding information within signals), and alsoincludes a decoder module therein for decoding signals that are received(e.g., decoding signals to make estimate of information encodedtherein).

Any of the various types and embodiments of encoding and/or decodingdescribed herein can be employed within any such desired communicationsystem (e.g., including those variations described with respect to FIG.1), any information storage device (e.g., hard disk drives (HDDs),network information storage devices and/or servers, etc.) or anyapplication in which information encoding and/or decoding is desired.

As mentioned above, while many different types of communication systemsare depicted with respect to various types of communication systems, anysuch communication system that includes at least one optical networkportion, segment, or communication link, etc. therein can employ variousaspects of the invention.

Referring to the communication system 200 of FIG. 2, at a transmittingend of a communication channel 299, information bits 201 are provided toa transmitter 297 that is operable to perform encoding of theseinformation bits 201 using an encoder and symbol mapper 220 (which maybe viewed as being distinct functional blocks 222 and 224, respectively)thereby generating a sequence of discrete-valued modulation symbols 203that is provided to a transmit driver 230 that uses a DAC (Digital toAnalog Converter) 232 to generate a continuous-time transmit signal 204and a transmit filter 234 to generate a filtered, continuous-timetransmit signal 205 that substantially comports with the communicationchannel 299. At a receiving end of the communication channel 299,continuous-time receive signal 206 is provided to an AFE (Analog FrontEnd) 260 that includes a receive filter 262 (that generates a filtered,continuous-time receive signal 207) and an ADC (Analog to DigitalConverter) 264 (that generates discrete-time receive signals 208). Ametric generator 270 calculates metrics 209 (e.g., on either a symboland/or bit basis) that are employed by a decoder 280 to make bestestimates of the discrete-valued modulation symbols and information bitsencoded therein 210.

The decoders and/or receiver portions of either of the previousembodiments may be implemented to include various aspects and/orembodiment of the invention therein. For example, considering theembodiment of FIG. 2, electronic dispersion compensation (EDC) circuitry290 is interposed between the ADC 264 of the AFE 260 and the metricgenerator 270. Alternatively, such EDC functionality could also beimplemented within other portions of the receiver 298 of the FIG. 2(e.g., within the decoder 280, or elsewhere therein). Such EDCfunctionality allows for performing compensation of optical incurreddeficiencies (e.g., dispersion, non-linearity, inter-symbol interference(ISI), etc.). Within a communication device's receiver portion,equalization and compensation is performed in the electronic domain asadapted for high speed applications and higher order modulation schemes.Compare this to attempting to perform such compensation in the opticaldomain within a receiver communication device. By performingequalization and compensation in the electronic domain (as opposed toattempting to perform such equalization and compensation in the opticaldomain), higher speed applications and advanced modulation schemes maybe properly addressed in accordance with the principles presentedherein.

In addition, several of the following Figures describe other andparticular embodiments (some in more detail) that may be used to supportthe devices, systems, functionality and/or methods that may beimplemented in accordance with certain aspects and/or embodiments of theinvention.

FIG. 3 illustrates an embodiment of an optical duobinary (ODB)communication system 300. In such an ODB communication system 300, anoriginal signal (e.g., source signal) is initially provided to aprecoding circuitry 310 that is operative to perform differentialencoding. After undergoing differential encoding in the precodingcircuitry 310, then the differential encoded signal undergoes duobinaryencoding in the differential encoding circuitry 320. Thereafter, theprecoded and duobinary encoded signal is provided to an electrical tooptical interface 330 (e.g., which may be implemented as any of avariety of light sources [such as a dual-drive Mach-Zehnder type opticalintensity modulator with push-pull operation, a light emitting diode(LED) or a laser diode (LD) whose output intensity may be modulated,etc.] suitable to generate an optical signal to be launched into anoptical communication link [such as an optical fiber]).

After the electrical signal is converted to an optical signal, theoptical signal is propagated through the optical communication link(e.g., an optical fiber) to the receiver side of the communicationchannel. On the receiver side, the optical signal is converted from anoptical signal to an electrical signal (e.g., using a photo-detectordevice such as a photo-diode that generates a current corresponding tothe intensity of the light striking the photo-sensitive service). Thisnow-generated electrical signal can go directly to a decision circuit(e.g., a hard limiter or slicer) to convert it to digital binary signal.Alternatively, the now-generated electrical signal can be provided to ananalog to digital converter (ADC) circuitry 350 and subsequently to anelectronic dispersion compensation (EDC) circuitry 360 for extra and/orsubsequent dispersion compensation to address any deficiencies that maybe incurred during transmission via the optical communication channel(e.g., inter-symbol interference (ISI), dispersion, or non-linearitycorresponding to or associated with one or more of the opticalcomponents of the optical communication channel or communicationsystem).

FIG. 4 illustrates an embodiment of an electronic dispersioncompensation (EDC) circuitry 400. This diagram shows a decision feedbackequalizer (DFE) type EDC circuitry in which a digital signal (e.g., suchas may be generated by an ADC or as may be output from some other typeof digital processing component) is initially provided to a feed forwardequalizer (FFE) 410. The FFE 410 is operative to equalize any pre-cursorISI. The output from the FFE 410 is operative to provide a signal to asummer circuitry that is operative to add a feedback signal to thesignal provided from the FFE 410. A slicer or hard limiter 430 isoperative to make a hard estimate for the signal provided from thesummer circuitry. From the slicer or hard limiter 430, the hard estimateis provided to a decision feedback equalizer (DFE) circuitry 440. TheDFE circuitry 440 is implemented after the decision circuit (e.g., theslicer or hard limiter 430) and is operative to remove the post-cursorISI that may be existent in the signal. The DFE circuitry 440 isoperative to generate the feedback signal provided back to the summercircuitry.

FIG. 5 illustrates an embodiment of an EDC circuitry 500 for an opticalduobinary (ODB) receiver communication device. This diagram shows theDFE type EDC circuitry as may be applied for use in an ODB communicationsystem.

A digital signal (e.g., such as may be generated by an ADC or as may beoutput from some other type of digital processing component) isinitially provided to a FFE 510. The FFE 510 is operative to equalizeany pre-cursor ISI. The output from the FFE 510 is operative to providea signal to a summer circuitry that is operative to add a feedbacksignal to the signal provided from the FFE 510. A slicer or hard limiter530 is operative to make a hard estimate for the signal provided fromthe summer circuitry. From the slicer or hard limiter 530, the hardestimate is provided to a reconstruction circuitry 590, that itselfincludes precoding circuitry 590 a and duobinary encoding circuitry 590b. The output of the reconstruction circuitry 590 is provided to a DFEcircuitry 540, which generates the feedback signal provided back to thesummer circuitry.

Because of the nature of an ODB communication system, there aretypically only two level of electric signals {0, 1} detected or employedat the receiver side of the communication channel, where actually {1}actually represents two possible optical field signals {+1, −1}. Inorder to compensate for optical impairments between {+1, −1},reconstruction of the duobinary encoded signal is performed. Therefore,differential encoding circuit and duobinary encoding is added after thedecision logic (shown as slicer or hard limiter 530).

For the differential encoding (precoding):d _(k) =c _(k) ⊕d _(k−1)  (1)

For the duobinary encoding:e _(k) =d _(k) +d _(k−1)−1  (2)

The DFE circuitry 540 has different coefficients between the {−1 +1}signals.

The above DFE mentioned DFE circuitry 540 may also modified by splittingthe DFE circuitry 540 into two separate and distinct DFE circuitries.

FIG. 6 illustrates an embodiment of an EDC circuitry 600 for an ODBreceiver communication device that employs two separate decisionfeedback equalizers (DFEs). This diagram has some similarities to theprevious embodiment, with at least one difference being that the DFEcircuitry 540 (of the previous embodiment) into two separate anddistinct DFE circuitries.

A digital signal (e.g., such as may be generated by an ADC or as may beoutput from some other type of digital processing component) isinitially provided to a FFE 610. The FFE 610 is operative to equalizeany pre-cursor ISI. The output from the FFE 610 is operative to providea signal to a summer circuitry that is operative to add a first feedbacksignal and a second feedback signal to the signal provided from the FFE610. A slicer or hard limiter 630 is operative to make a hard estimatefor the signal provided from the summer circuitry. From the slicer orhard limiter 630, the hard estimate is provided to a reconstructioncircuitry 690 and also simultaneously to a DFE1 circuitry 640, whichgenerates a first of the two feedback signals provided back to thesummer circuitry. The reconstruction circuitry 690 includes precodingcircuitry 690 a and duobinary encoding circuitry 690 b. The output ofthe reconstruction circuitry 690 is provided to an incremental DFE2circuitry 695, which generates a second of the two feedback signalsprovided back to the summer circuitry.

The EDC circuitry 600 may be implemented within a communication device(e.g., generally referred to as an apparatus) that is operative toreceive an optical signal from an optical communication channel. Such acommunication device may include an optical to electrical interfacecircuitry that is operative to process the optical signal therebygenerating an electrical signal, and the communication device may alsoinclude an ADC that is operative to sample the electrical signal therebygenerating a first digital signal. The EDC circuitry 600, operating inan electronic domain, is operative to process the first digital signalthereby generating a second digital signal that is emulative of theoptical signal, and to equalize the second digital signal in the seconddigital signal to compensate for at least one deficiency correspondingto the optical signal.

Comparing this diagram to the previous embodiment, this diagram shows aDFE type EDC circuitry with a split DFE (e.g., two separate and distinctDFE circuitries). The major DFE1 circuitry 640 is analogous and similarto the DFE circuitry 540 of the previous embodiment while theincremental DFE2 circuitry 695 is operative to compensate for thedifference between {−1, +1} signals.

It is noted that certain embodiments may also employ a maximumlikelihood sequence detection (MLSD) scheme (e.g., as described inreference [7]) to determine the sequence of data symbols that bestmatches an observed sequence of signal samples that have been corruptedby noise and interference. A common implementation of an MLSD schemeinvolves the Viterbi algorithm or a Viterbi detection approach. A MLSDtype EDC for optical fiber communication has been demonstrated inreference [8].

For an ODB communication system, the use of MLSD necessarily increasesthe overall complexity of a communication device implemented within sucha communication system. Instead of two levels of signals beingassociated with each incoming symbol, there are instead three levels ofthe signal. To make the situation even more complex, not all sequencesformed using the three distinct levels of signals {0, −1, +1} areallowable or legal in accordance with the encoding process. For example,the sequence having a transition from “−1, +1” is not an allowed orlegal sequence in accordance with the encoding process.

By adding a reconstruction circuitry (e.g., such as reconstructioncircuitry 690) in the receiver, the channel estimator operation can bewritten as:y _(n)=β(e _(n+m) ,e _(n+m−1) , . . . ,e _(n−m+1))=β(d _(n−m+1) ,c_(n+m) ,c _(n+m−1) , . . . ,c _(n−m+1))  (3)

Above, as also depicted in the diagram, the variables associated with care being output from the slicer or hard limiter 630, the variablesassociated with e are being output from the reconstruction circuitry690. In addition, the variables associated with d are being output fromthe precoding circuitry 690 a that is implemented within thereconstruction circuitry 690.

Where the relationship between e and d, c follows from equation (1) and(2) and we also assume at time n, the channel response depends on the mbits appearing before and the m bits appearing after time n in path.

A Viterbi detector or Viterbi algorithm can be applied directly afterthis modified channel estimator.

FIG. 7 illustrates an embodiment of an optical differential phase shiftkeying (DSPK) communication system 700. In such a DSPK communicationsystem 700, an original signal (e.g., source signal) is initiallyprovided to a precoding circuitry 710 that is operative to performdifferential encoding. After undergoing differential encoding in theprecoding circuitry 710, then the differential encoded signal isprovided to an electrical to optical interface 730 (e.g., which may beimplemented as any of a variety of light sources [such as a dual-driveMach-Zehnder type optical intensity modulator with push-pull operation,a light emitting diode (LED) or a laser diode (LD) whose outputintensity may be modulated, etc.] suitable to generate an optical signalto be launched into an optical communication link [such as an opticalfiber]).

After the electrical signal is converted to an optical signal, theoptical signal is propagated through the optical communication link(e.g., an optical fiber) to the receiver side of the communicationchannel. On the receiver side, the optical signal is first demodulatedby delay line interferometer (shown as T in the diagram). Thereafter,the optical signal is converted to electrical signal using directdetector (DD) or balanced detector type device. For example, such a DDor balanced detector type device is used to convert the optical signalto an electrical signal.

This now-generated electrical signal can go directly to a decisioncircuit (e.g., a hard limiter or slicer) to convert it to digital binarysignal. Alternatively, the now-generated electrical signal can beprovided to an analog to digital converter (ADC) circuitry 750 andsubsequently to an electronic dispersion compensation (EDC) circuitry760 for extra and/or subsequent dispersion compensation to address anydeficiencies that may be incurred during transmission via the opticalcommunication channel (e.g., inter-symbol interference (ISI),dispersion, or non-linearity corresponding to or associated with one ormore of the optical components of the optical communication channel orcommunication system).

FIG. 8 illustrates an embodiment of an EDC circuitry 800 for a DSPKreceiver communication device that employs two separate DFEs. A digitalsignal (e.g., such as may be generated by an ADC or as may be outputfrom some other type of digital processing component) is initiallyprovided to a FFE 810. The FFE 810 is operative to equalize anypre-cursor ISI. The output from the FFE 810 is operative to provide asignal to a summer circuitry that is operative to add a first feedbacksignal and a second feedback signal to the signal provided from the FFE810. A slicer or hard limiter 830 is operative to make a hard estimatefor the signal provided from the summer circuitry. From the slicer orhard limiter 830, the hard estimate is provided to a reconstructioncircuitry for DD 890 and also simultaneously to a precoding circuitry892. The output from the precoding circuitry 892 is provided to DFE1circuitry 840, which generates a first of the two feedback signalsprovided back to the summer circuitry. The reconstruction circuitry forDD 890 includes precoding circuitry 890 a and duobinary encodingcircuitry 890 b. The output of the reconstruction circuitry 890 isprovided to DFE2 circuitry 895, which generates a second of the twofeedback signals provided back to the summer circuitry.

As described with reference to other embodiments, the EDC circuitry 800may be implemented within a communication device (e.g., generallyreferred to as an apparatus) that is operative to receive an opticalsignal from an optical communication channel. Such a communicationdevice may include an optical to electrical interface circuitry that isoperative to process the optical signal thereby generating an electricalsignal, and the communication device may also include an ADC that isoperative to sample the electrical signal thereby generating a firstdigital signal. The EDC circuitry 800, operating in an electronicdomain, is operative to process the first digital signal therebygenerating a second digital signal that is emulative of the opticalsignal, and to equalize the second digital signal in the second digitalsignal to compensate for at least one deficiency corresponding to theoptical signal.

In this diagram, two separate and distinct DFE circuitries areimplemented (e.g., depicted as DFE1 840 and DFE2 895). DFE1 circuitry840 is operative to compensate the impairment due to communication overthe optical fiber. DEF2 circuitry 895 is operative to compensate theimpairment due to electronic components within the apparatus (e.g., suchas a photo detector or photo diode, ADC circuitry, etc.). Because theoptical signal over the fiber is a precoded signal and therefore, thesignal is reconstructed using the precoding logic in accordance with thereconstruction logic circuitry for DD 890.

In this diagram, the reconstruction logic circuitry for DD 890 isimplemented for a direct detector. If it is not implemented for a DDtype device, the difference between +1 and −1 may be not be adequatelycompensated. Alternatively, for a balanced detector, such operation isnot needed.

FIG. 9 illustrates an embodiment of a constellation plane 900 fordifferential quadrature phase shift keying (DQSPK) modulation. A DQPSKtransmission scheme accumulates 2 bits per symbol, so 4 symbols aretransmitted over the optical communication channel (e.g., optical fiber)per symbol. This diagram shows the constellation plane of such a DQPSKsystem. DQPSK can be considered to combine two DPSK channels together,one is an in-phase (I) channel which is in phase and the other is aquadrature (Q) channel which is at quadrature phase. In such anapplication, a balanced detector is typically used.

FIG. 10 illustrates an embodiment of an EDC circuitry 1000 for a DQSPKreceiver communication device that employs three separate DFEs. Thisdiagram shows the DFE type equalizer as may be applied for optical DQPSKsystem.

A digital signal (e.g., such as may be generated by an ADC or as may beoutput from some other type of digital processing component) is composedof an in-phase (I) digital signal component and a quadrature (Q) digitalsignal component. The in-phase (I) digital signal (e.g., such asprovided from an ADC or other digital processing component) is initiallyprovided to a first FFE1 1010 a. The quadrature (Q) digital signal(e.g., such as provided from an ADC or other digital processingcomponent) is initially provided to a second FFE2 1010 b.

A first summer circuitry, coupled to the first FFE1 1010 a, is operativeto sum the processed, in-phase digital signal output from the first FFE11010 a with a first feedback signal thereby generating a first summedsignal. A first slicer or hard limiter circuitry 1030 a, coupled to thefirst summer circuitry, is operative to generate a first hard estimatecorresponding to the first summed signal. A DFE2 circuitry 1042, coupledto the first slicer or hard limiter circuitry 1030 a, is operative toprocess the first hard estimate thereby generating a first equalizedsignal.

A precoding circuitry 1090, coupled to the first slicer or hard limitercircuitry 1030 a, that is operative to process the first hard estimatethereby generating a precoded in-phase signal. DFE1 circuitry 1041,coupled to the precoding circuitry 1090, is operative to process theprecoded in-phase signal thereby generating a second feedback signal.

A second summer circuitry, coupled to the DFE1 circuitry 1041 and theDFE2 circuitry 1042, is operative to sum the first equalized signal andthe second feedback signal thereby generating the first feedback signal.

A second FFE2 1010 b is operative to process the quadrature (Q) digitalsignal component. A third summer circuitry, coupled to the second FFE21010 b, is operative to sum the processed, quadrature digital signaloutput from the second FFE2 1010 b with a third feedback signal therebygenerating a second summed signal. A second slicer or hard limitercircuitry 1030 b, coupled to the third summer circuitry, is operative togenerate a second hard estimate corresponding to the second summedsignal. A DFE3 circuitry 1043, coupled to the second slicer or hardlimiter circuitry 1030 b, is operative to process the second hardestimate thereby generating a second equalized signal.

The precoding circuitry 1090, being also coupled to the second slicer orhard limiter circuitry 1030 b, is operative to process the second hardestimate thereby generating a precoded quadrature signal. The DFE3circuitry 1043 is also operative to process the precoded quadraturesignal thereby generating a fourth feedback signal. A fourth summercircuitry, coupled to the DFE1 circuitry 1041 and the DFE3 circuitry1043, that is operative to sum the second equalized signal and thefourth feedback signal thereby generating the third feedback signal.

As described with reference to other embodiments, the EDC circuitry 1000may be implemented within a communication device (e.g., generallyreferred to as an apparatus) that is operative to receive an opticalsignal from an optical communication channel. Such a communicationdevice may include an optical to electrical interface circuitry that isoperative to process the optical signal thereby generating an electricalsignal, and the communication device may also include an ADC that isoperative to sample the electrical signal thereby generating a firstdigital signal. The EDC circuitry 1000, operating in an electronicdomain, is operative to process the first digital signal therebygenerating a second digital signal that is emulative of the opticalsignal, and to equalize the second digital signal in the second digitalsignal to compensate for at least one deficiency corresponding to theoptical signal.

In this diagram, three DFEs (DFE1 circuitry 1041, DFE2 circuitry 1042,and the DFE3 circuitry 1043) are shown in the system. DFE1 circuitry1041 is operative to compensate the impairment due to communication overthe optical fiber. DFE2 circuitry 1042 and DFE3 circuitry 1043 areoperative to compensate any impairment that may be due to electroniccomponents within the apparatus (e.g., as maybe generated by a photodetector or photo diode and/or ADC circuitry) for each of the I channeland Q channel, respectively. Because the optical signal transmitted overthe optical communication link (e.g., the optical fiber) is precodedsignal and therefore, the signal may be reconstructed using precodinglogic (alternative embodiments of such are described in reference [9]):I _(k) =a _(k) b _(k) I _(k−1) +a _(k) b _(k) Q _(k−1) +ā _(k) b _(k) Ī_(k−1) +ā _(k) b _(k) Q _(k−1)  (4)Q _(k) =a _(k) b _(k) Q _(k−1) +a _(k) b _(k) Ī _(k−1) +ā _(k) b _(k) Q_(k−1) +ā _(k) b _(k) I _(k−1)  (5)

In the diagram, a balanced detector is assumed and, as such, there is noneed for reconstruction logic circuitry therein.

For an MLSD type EDC circuitry as applied for a DPSK/DQPSK communicationsystem, the architecture it is similar to MLSD type EDC for ODB system.As the case for the DFE type EDC for DPSK/DQPSK, the channel estimatorcan be partitioned/split into two parts:y _(n)=β1+β2  (6)

While β1 is the channel estimator from the fiber part, which is thedirect function of the precoded signal, and β2 is the channel estimatorfrom the photo detector and other parts which is the direct function ofdecoded signal for balanced detector.

For design using LMS (least mean square) error (as described inreference [6], the corresponding U.S. utility patent application ofwhich is incorporated herein by reference above) to do timing recovery,channel estimation is performed. Accurate channel estimation alsoemploys a reconstruction logic circuit for ODB/DPSK/DQPSK, similar tothe case for MLSD type EDC.

FIG. 11A and FIG. 11B illustrate various embodiments of methods 1100 and1101 for performing electronic dispersion compensation in the electronicdomain using reconstruction for a communication device implementedwithin an optical communication system.

Referring to method 1100 of FIG. 11A, the method 1100 begins byreceiving an optical signal from an optical communication channel, asshown in a block 1110. While this communication channel may be opticalin nature, it is noted that there may be other communication linkswithin the communication system that may be implemented usingalternative types of technology (e.g., wireless communication links,wired communication links, etc.). The method 1100 continues by employingan optical to electrical interface circuitry to process the opticalsignal thereby generating an electrical signal, as shown in a block1120. This process may be viewed as performing optical to electronicconversion of a signal such as using a photo-detector circuitry(alternatively, referred to as a photo-diode circuitry).

The method 1100 then operates by employing an analog to digitalconverter (ADC) to sample the electrical signal thereby generating afirst digital signal, as shown in a block 1130. Generally speaking, thisoperation corresponds to performing digital sampling of a continuoustime signal as generated by and output from the optical to electricalinterface circuitry.

As shown in a block 1140, the method 1100 then operates by employing anelectronic dispersion compensation (EDC) circuitry, being coupled to theADC, to perform electronic domain compensation for one or moredeficiencies (e.g., inter-symbol interference (ISI), dispersion, andnon-linearity, etc.) that is associated with the optical signal receivedfrom the optical communication channel. Generally, such deficienciesassociated with the optical signal are incurred with imperfections ofthe optical communication channel and/or optical hardware componentsimplemented in and associated with the optical communication system thatincludes the optical communication channel. The operation of the block1140 operates to process the first digital signal thereby generating asecond digital signal that is emulative of the optical signal (e.g., theone received from the from optical communication channel. The operationof the block 1140 also operates to process equalize the second digitalsignal in the second digital signal to compensate for at least onedeficiency corresponding to the optical signal.

Referring to method 1101 of FIG. 11B, the method 1101 begins byemploying a feed forward equalizer (FFE) to process a first digitalsignal provided from an ADC, as shown in a block 1111. Generallyspeaking, the first digital signal output from the ADC may be viewed asa digital signal generated by performing digital sampling of acontinuous time signal as generated by and output from an optical toelectrical interface circuitry. The FFE is operative to equalizepost-cursor ISI that may be existent within an optical signal that isreceived from an optical communication channel.

The method 1101 then operates by employing a summer circuitry, coupledto the FFE, to sum the processed, first digital signal output from theFFE with a first feedback signal and a second feedback signal therebygenerating a summed signal, as shown in a block 1121. The first feedbacksignal and the second feedback signal are generated as described below.The method 1101 continues by employing a hard limiter circuitry, coupledto the summer circuitry, to generate a hard estimate corresponding tothe summed signal, as shown in a block 1131. A hard limiter mayalternatively be referred to as a slicer.

The method 1101 then operates by employing a first decision feedbackequalizer (DFE), coupled to the hard limiter circuitry, to process thehard estimate thereby generating the first feedback signal (e.g., thatis employed and referenced in the block 1121), as shown in a block 1141.The method 1101 then operates by employing a reconstruction circuitry,coupled to the hard limiter circuitry, to process the hard estimatethereby generating a reconstructed signal, as shown in a block 1151.

The method 1101 continues by employing a second DFE, coupled to thereconstruction circuitry, to process the reconstructed signal therebygenerating the second feedback signal (e.g., that is employed andreferenced in the block 1121), as shown in a block 1161.

It is noted that the operations as performed by the reconstructioncircuitry (e.g., such as those performed and referenced in the block1151) may also involve employing a precoding circuitry (being acomponent of the reconstruction circuitry) to process the hard estimatethereby generating a precoded signal. In addition, the operations asperformed by the reconstruction circuitry (e.g., such as those performedand referenced in the block 1151) may also involve employing a duobinaryencoding circuitry (also being a component of the reconstructioncircuitry) to process the precoded signal thereby generating thereconstructed signal.

It is noted that the various modules (e.g., encoding modules, decodingmodules, reconstruction circuitries, decision feedback equalizers (DFEs)precoding circuitries, duobinary encoding circuitries, etc.) describedherein may be a single processing device or a plurality of processingdevices. Such a processing device may be a microprocessor,micro-controller, digital signal processor, microcomputer, centralprocessing unit, field programmable gate array, programmable logicdevice, state machine, logic circuitry, analog circuitry, digitalcircuitry, and/or any device that manipulates signals (analog and/ordigital) based on operational instructions. The operational instructionsmay be stored in a memory. The memory may be a single memory device or aplurality of memory devices. Such a memory device may be a read-onlymemory, random access memory, volatile memory, non-volatile memory,static memory, dynamic memory, flash memory, and/or any device thatstores digital information. It is also noted that when the processingmodule implements one or more of its functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, the memorystoring the corresponding operational instructions is embedded with thecircuitry comprising the state machine, analog circuitry, digitalcircuitry, and/or logic circuitry. In such an embodiment, a memorystores, and a processing module coupled thereto executes, operationalinstructions corresponding to at least some of the steps and/orfunctions illustrated and/or described herein.

The present invention has also been described above with the aid ofmethod steps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid offunctional building blocks illustrating the performance of certainsignificant functions. The boundaries of these functional buildingblocks have been arbitrarily defined for convenience of description.Alternate boundaries could be defined as long as the certain significantfunctions are appropriately performed. Similarly, flow diagram blocksmay also have been arbitrarily defined herein to illustrate certainsignificant functionality. To the extent used, the flow diagram blockboundaries and sequence could have been defined otherwise and stillperform the certain significant functionality. Such alternatedefinitions of both functional building blocks and flow diagram blocksand sequences are thus within the scope and spirit of the claimedinvention.

One of average skill in the art will also recognize that the functionalbuilding blocks, and other illustrative blocks, modules and componentsherein, can be implemented as illustrated or by discrete components,application specific integrated circuits, processors executingappropriate software and the like or any combination thereof.

Moreover, although described in detail for purposes of clarity andunderstanding by way of the aforementioned embodiments, the presentinvention is not limited to such embodiments. It will be obvious to oneof average skill in the art that various changes and modifications maybe practiced within the spirit and scope of the invention, as limitedonly by the scope of the appended claims.

REFERENCES

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What is claimed is:
 1. An apparatus, comprising: an input to receive anoptical signal from an optical communication channel; an optical toelectrical interface circuitry to process the optical signal to generatean electrical signal; an analog to digital converter (ADC) to sample theelectrical signal to generate a first digital signal; an electronicdispersion compensation (EDC) circuitry, coupled to the ADC, that, in anelectronic domain, is configured to: process the first digital signal,via a feed forward equalizer (FFE), to generate a first digital signaloutput; sum, via a summer circuitry, the first digital signal outputwith a first feedback signal and a second feedback signal to generate asummed signal, wherein a first decision feedback equalizer (DFE)circuitry processes a hard estimate to produce the first feedbacksignal, and a second DFE circuitry processes a reconstructed signal toproduce the second feedback signal; generate the hard estimate, via ahard limiter circuitry, corresponding to the summed signal; generate asecond digital signal emulative of the optical signal based on the firstdigital signal and the second feedback signal; and equalize the seconddigital signal to compensate for at least one deficiency correspondingto the optical signal; and a reconstruction circuitry to process thehard estimate to generate the reconstructed signal, the reconstructioncircuitry including: a precoding circuitry to process the hard estimateto generate a precoded signal; and a duobinary encoding circuitry,coupled to the precoding circuitry, to process the precoded signal togenerate the reconstructed signal.
 2. The apparatus of claim 1, wherein:the first DFE circuitry to compensate for inter-symbol interference(ISI) associated with the optical signal; and the second DFE circuitryto compensate for a difference between a maximum value and a minimumvalue associated with the summed signal.
 3. The apparatus of claim 1,wherein: the at least one deficiency corresponding to the optical signalis inter-symbol interference (ISI), dispersion, or non-linearitycorresponding to or associated with at least one optical component ofthe optical communication channel.
 4. The apparatus of claim 1, wherein:the apparatus is a transceiver or a receiver.
 5. An apparatus,comprising: an input to receive an optical signal from an opticalcommunication channel; an optical to electrical interface circuitry toprocess the optical signal thereby generating an electrical signal; ananalog to digital converter (ADC) to sample the electrical signalthereby generating a digital signal including at least one deficiencycorresponding to the optical signal, wherein the at least one deficiencyis inter-symbol interference (ISI), dispersion, or non-linearitycorresponding to or associated with at least one optical component ofthe optical communication channel; and a feed forward equalizer (FFE),coupled to the ADC, to process the digital signal and to compensate forthe at least one deficiency to produce a processed digital signaloutput; a summer circuitry, coupled to the FFE, to sum the processeddigital signal output from the FFE with a first feedback signal and asecond feedback signal thereby generating a summed signal; a hardlimiter circuitry, coupled to the summer circuitry, to generate a hardestimate corresponding to the summed signal; a first decision feedbackequalizer (DFE) circuitry, coupled to the hard limiter circuitry, toprocess the hard estimate thereby generating the first feedback signal;a reconstruction circuitry, coupled to the hard limiter circuitry, toprocess the hard estimate thereby generating a reconstructed signal,wherein the reconstruction circuitry including: a precoding circuitry toprocess the hard estimate thereby generating a precoded signal; and aduobinary encoding circuitry, coupled to the precoding circuitry, toprocess the precoded signal thereby generating the reconstructed signal;and a second DFE circuitry, coupled to the reconstruction circuitry, toprocess the reconstructed signal thereby generating the second feedbacksignal.
 6. The apparatus of claim 5, wherein: the apparatus includes ahard disk drive (HDD).
 7. The apparatus of claim 5, wherein: the firstDFE circuitry is configured to compensate for the at least onedeficiency being ISI; and the second DFE circuitry is configured tocompensate for a difference between a maximum value and a minimum valueassociated with the summed signal.
 8. The apparatus of claim 5, wherein:the apparatus is a transceiver or a receiver.
 9. A method, comprising:receiving an optical signal from an optical communication channel;employing an optical to electrical interface circuitry to process theoptical signal to generate an electrical signal; employing an analog todigital converter (ADC) to sample the electrical signal to generate afirst digital signal; within an electronic domain, employing anelectronic dispersion compensation (EDC) circuitry, coupled to the ADC,to: process the first digital signal, via a feed forward equalizer(FFE), to generate a first digital signal output; sum, via a summercircuitry, the first digital signal output with a first feedback signaland a second feedback signal to generate a summed signal, wherein afirst decision feedback equalizer (DFE) circuitry processes a hardestimate to produce the first feedback signal, and a second DFEcircuitry processes a reconstructed signal to produce the secondfeedback signal; generate the hard estimate, via a hard limitercircuitry, corresponding to the summed signal; generate a second digitalsignal emulative of the optical signal based on the first digital signaland the second feedback signal; and equalize the second digital signalto compensate for at least one deficiency corresponding to the opticalsignal; and employing a reconstruction circuitry to process the hardestimate to generate the reconstructed signal by: employing a precodingcircuitry to process the hard estimate to generate a precoded signal;and employing a duobinary encoding circuitry, coupled to the precodingcircuitry, to process the precoded signal to generate the reconstructedsignal.
 10. The method of claim 9, wherein: the at least one deficiencycorresponding to the optical signal is inter-symbol interference (ISI),dispersion, or non-linearity corresponding to or associated with atleast one optical component of the optical communication channel. 11.The method of claim 9, wherein: the method is performed within acommunication device; and the communication device is a transceiver or areceiver.
 12. The apparatus of claim 1, wherein: the apparatus being acommunication device operative within a fiber-optic communication systemand also operative within at least one of a satellite communicationsystem, a wireless communication system, and a wired communicationsystem.
 13. The apparatus of claim 5, wherein: the apparatus being acommunication device operative within a fiber-optic communication systemand also operative within at least one of a satellite communicationsystem, a wireless communication system, and a wired communicationsystem.
 14. The method of claim 9, wherein: the method is performedwithin a communication device that is operative within a fiber-opticcommunication system and also operative within at least one of asatellite communication system, a wireless communication system, and awired communication system.
 15. The method of claim 9, wherein: thefirst DFE circuitry to compensate for inter-symbol interference (ISI)associated with the optical signal; and the second DFE circuitry tocompensate for a difference between a maximum value and a minimum valueassociated with the summed signal.
 16. The apparatus of claim 1, whereinthe apparatus comprises an optical duobinary (ODB) receivercommunication device.
 17. The apparatus of claim 1, wherein the firstDFE circuitry and the second DFE circuitry are configured as a split DFEcircuitry.
 18. The apparatus of claim 1, wherein: the apparatus includesa hard disk drive (HDD).
 19. The apparatus of claim 5, wherein theapparatus comprises an optical duobinary (ODB) receiver communicationdevice.
 20. The apparatus of claim 5, wherein the first DFE circuitryand the second DFE circuitry are configured as a split DFE circuitry.